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Flexible static memory controller (FSMC)
RM0008
19.6.2
NAND Flash / PC Card supported memories and transactions
Table 117 below shows the supported devices, access modes and transactions.
Transactions not allowed (or not supported) by the NAND Flash / PC Card controller appear
in gray.
Table 117. Supported memories and transactions
Device
Mode
R/W
AHB Memory Allowed/
data size data size not allowed
Comments
Asynchronous
Asynchronous
R
W
8
8
8
8
Y
Y
Asynchronous
R
16
8
Y
Split into 2 FSMC accesses
NAND 8-bit
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
W
R
W
R
W
R
16
32
32
8
8
16
8
8
8
16
16
16
Y
Y
Y
Y
N
Y
Split into 2 FSMC accesses
Split into 4 FSMC accesses
Split into 4 FSMC accesses
NAND 16-bit
Asynchronous
W
16
16
Y
Asynchronous
Asynchronous
R
W
32
32
16
16
Y
Y
Split into 2 FSMC accesses
Split into 2 FSMC accesses
19.6.3
Timing diagrams for NAND, ATA and PC Card
Each PC Card/CompactFlash and NAND Flash memory bank is managed through a set of
registers:
●
●
●
●
●
●
Control register: FSMC_PCRx
Interrupt status register: FSMC_SRx
ECC register: FSMC_ECCRx
Timing register for Common memory space: FSMC_PMEMx
Timing register for Attribute memory space: FSMC_PATTx
Timing register for I/O space: FSMC_PIOx
Each timing configuration register contains three parameters used to define number of
HCLK cycles for the three phases of any PC Card/CompactFlash or NAND Flash access,
plus one parameter that defines the timing for starting driving the databus in the case of a
write. Figure 175 shows the timing parameter definitions for common memory accesses,
knowing that Attribute and I/O (only for PC Card) memory space access timings are similar.
444/995
Doc ID 13902 Rev 9
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